Search Results - aviral+shrivastava

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Accurate Cooperative Sensor Fusion by Parameterized Covariance Generation for Sensing and Localization Pipelines in CAVs
Background Cooperative sensing is used to mitigate sensor coverage and obstruction issues in autonomous vehicles. Cooperative sensing happens when multiple connected autonomous vehicles (CAVs) combine data to gain a more accurate picture of the world around each individual CAV. Additional connected infrastructure sensors (CISs) placed throughout a...
Published: 4/10/2024   |   Inventor(s): Edward Andert, Aviral Shrivastava
Keywords(s):  
Category(s): Wireless & Networking, Physical Science, Manufacturing/Construction/Mechanical, Applied Technologies
PathSeeker: A Fast-Mapping Algorithm for CGRAs
The rapid advancement of the internet and data-collecting devices has sparked increasing demand for computing solutions that are both energy-efficient and high-performance. Coarse-grained reconfigurable arrays (CGRAs) have gained traction as this low-power alternative, offering accelerators capable of supporting the compute-intensive process of collecting,...
Published: 11/22/2023   |   Inventor(s): Mahesh Balasubramanian, Aviral Shrivastava
Keywords(s): Algorithm Development, Machine Learning, Neural Computing, PS-Computing and Information Technology
Category(s): Computing & Information Technology, Physical Science
Explainable Design Space Exploration for Efficient Hardware/Software Codesigns
Computing system designers need to characterize the execution of applications on a computing system (e.g., on a processor) and they also need to improve the design (i.e., find better hardware/software configurations for the computing system such as one that produces more throughput at lower energy consumption). Existing mechanisms for computing systems’...
Published: 10/18/2023   |   Inventor(s): Shail Dave, Aviral Shrivastava, Tony Nowatzki
Keywords(s): Performance Optimization, PS-Computing and Information Technology
Category(s): Computing & Information Technology, Physical Science
Dynamic and Efficient Hardware/Software Codesigns of Deep Learning Accelerators
Efficient hardware/software codesigns of deep learning accelerators are crucial for optimizing their performance in various applications, ranging from datacenters to mobile and wearable devices. The existing methods for optimizing deep learning accelerator designs are primarily black-box approaches, which do not consider crucial information about the...
Published: 9/27/2023   |   Inventor(s): Shail Dave, Aviral Shrivastava
Keywords(s): Algorithm Development, Computing Architecture, Machine Learning, PS-Computing and Information Technology, Software
Category(s): Computing & Information Technology, Physical Science
Effective Triplication for Flexible and Real-Time Soft Error Resilience
­Background The increasing use of digital systems in everyday life has made reliability a key factor in the design of modern microprocessors. Soft errors are caused by high-energy particles, power supply noises, transistor variability, and can modify the logic value stored in microprocessor memory elements, which can cause a timing or functional...
Published: 2/23/2023   |   Inventor(s): Moslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj Lokam
Keywords(s):  
Category(s): Medical Devices, Computing & Information Technology, Wireless & Networking, Physical Science
Cooperative Driving of Connected Autonomous Vehicles Using Responsibility-Sensitive Safety Rules
­Background Connected Autonomous Vehicles (CAVs) are expected to enable reliable and efficient transportation systems. Most cooperative driving approaches for CAVs and motion planning algorithms for multi-agent systems are not completely safe because they implicitly assume that all vehicles/agents will execute the expected plan within a small margin...
Published: 2/23/2023   |   Inventor(s): Mohammad Khayatian, Mohammadreza Mehrabian, Harshith Allamsetti, Kai-Wei Liu, Po-Yu Huang, Chung-Wei Lin, Aviral Shrivastava
Keywords(s):  
Category(s): Wireless & Networking, Physical Science, Computing & Information Technology, Intelligence & Security
Improved Mapping of Computational Loops on Reconfigurable Architectures
Today there are numerous devices that collect, process, and communicate data from multiple sources such as the internet, cyber-physical and autonomous systems, and sensor networks. Extracting intelligent and actionable information from this data—whether done by machine learning or otherwise—is extremely compute-intensive and often limited...
Published: 12/18/2023   |   Inventor(s): Mahesh Balasubramanian, Aviral Shrivastava
Keywords(s): Algorithm Development, Machine Learning, Neural Computing, PS-Computing and Information Technology
Category(s): Physical Science, Computing & Information Technology
Extremely Lightweight Checkpoint Method for Resilience Against Soft Errors
Background Soft errors or transient faults—caused by high-energy particles that lead to an unexpected change in the transistor logic—have long been considered the main reliability challenge for many mission-critical applications. Conventionally, hardware-level soft-error resilience techniques have been employed in mission- and safety-critical...
Published: 2/23/2023   |   Inventor(s): Moslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj Lokam
Keywords(s):  
Category(s): Physical Science, Computing & Information Technology, Intelligence & Security
An infrastructure for memory management on LLM multi-core architectures
Limited Local Memory (LLM) multi-core architectures substitute cache with scratch pad memories (SPM). As a result, SPMs have much lower power consumption compared to other multi-core architectures. However, SPMs lack an automatic memory management system which presents a challenge to programmers as heap data sizes may be variable and data dependent....
Published: 2/23/2023   |   Inventor(s): Ke Bai, Aviral Shrivastava
Keywords(s): Algorithm Development, Cyber-Physical System, Memory, Simulation, Software
Category(s): Wireless & Networking
An Efficient Stack Data Management for Scratchpad Memory based Multi-core Processors
As technology scales, the number of cores in processors will rapidly increase in order to avoid the power wall. In processors that have hundreds and thousands of cores, traditional memory architectures – in which a coherent memory interface is provided to all the cores in hardware, will not be feasible. The memory management functionality is expected...
Published: 2/23/2023   |   Inventor(s): Ke Bai, Jing Lu, Aviral Shrivastava
Keywords(s): Algorithm Development, Cyber-Physical System, Memory, Software
Category(s): Computing & Information Technology
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