Search Results - sarma+vrudhula

15 Results Sort By:
In-Memory Hardware-Software Co-design for Image Processing
A substantial part of high energy consumption (> 60%) and large latency (> 90%) of conventional von-Neumann architectures can be attributed to the unavoidable data movement between the processor and main memory (DRAM). This is perhaps the major limiting factor for big data and machine learning applications whose usage is permeating into practically...
Published: 5/22/2024   |   Inventor(s): Ayushi Dube, Ankit Wagle, Gian Singh, Sarma Vrudhula
Keywords(s): Algorithm Development, Computing Architecture, Imaging, Machine Learning, Performance Optimization, PS-Computing and Information Technology, Resource Management
Category(s): Computing & Information Technology, Imaging, Physical Science
Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking
Synchronous logic remains the dominant design paradigm of digital systems such as Application Specific Integrated Circuits (ASICs). The conventional design of sequential circuit networks is based on the assumption that every register receives the clock signal at the same time. However, guaranteeing the simultaneity of clock arrival times in practice...
Published: 1/10/2024   |   Inventor(s): Sarma Vrudhula, Ankit Wagle
Keywords(s): Circuits, Computing Architecture, Electronics, Integrated Circuits, PS-Applied Technologies, PS-Semiconductor Devices
Category(s): Applied Technologies, Physical Science, Semiconductor Devices
Non-Volatile Logic Device for Energy-Efficient Logic State Restoration
Background Microelectronic circuits that obtain their energy from ambient energy sources (AES) through scavenging or harvesting are increasing in popularity, particularly with the burgeoning field of the Internet of Things (IoT). Some of the more common AES include solar, piezoelectric, vibration, airflow, and thermoelectric. The intermittent nature...
Published: 5/22/2024   |   Inventor(s): Jinghua Yang, Sarma Vrudhula, Aykut Dengi
Keywords(s):  
Category(s): Computing & Information Technology, Physical Science, Semiconductor Devices
FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power, and Area
Invention Description Implementation of lookup tables (LUTs) in a field-programmable gate array (FPGA) comes at the heavy cost of area, power, and performance. Researchers at Arizona State University have developed an alternative FPGA tile structure that consists of three traditional LUTs combined with a new reconfigurable threshold logic cell (TLC)....
Published: 5/22/2024   |   Inventor(s): Sarma Vrudhula, Ankit Wagle
Keywords(s):  
Category(s): Physical Science, Computing & Information Technology, Semiconductor Devices, Semiconductors, Materials & Processes
Performance and Energy Optimal DVFS, Task Migration and Active Cooling for Multi-core Processors
Multi-core processors have become the de facto standard of computing systems in all market segments: smartphones, laptops, desktops, and servers. A fundamental problem is being able to control the operation of the individual cores so as to maximize some suitably chosen measure of quality of service. Often, the primary goal in the design of any computing...
Published: 2/23/2023   |   Inventor(s): Vinay Hanumaiah, Sarma Vrudhula
Keywords(s): Networks, IT, Software and Communication
Category(s): Computing & Information Technology
Temperature-aware Robust Controller for Multi-core Processors
The transition to multi-core processors has allowed their continued improvement within their limited power budget by using threads on multiple cores. By reducing the power per core and increasing the number of cores initially allowed, it is possible to circumvent the power wall of single core processors. Unfortunately, multi-core scaling is fast becoming...
Published: 2/23/2023   |   Inventor(s): Vinay Hanumaiah, Sarma Vrudhula, Benjamin Gaudette
Keywords(s): Networks, IT, Software and Communication
Category(s): Computing & Information Technology
A Robust Low Power Field Programmable Threshold Logic Gate Array
Existing complementary metal-oxide-semiconductor (CMOS) technologies are becoming obsolete because we have nearly reached the maximum capability of further miniaturizing computer chips built from modern, state-of-the-art materials. The semiconductor industry association predicts that further scaling is not sustainable and new technologies that can replace...
Published: 2/23/2023   |   Inventor(s): Sarma Vrudhula, Niranjan Kulkarni
Keywords(s): Networks, IT, Software and Communication
Category(s): Semiconductor Devices
RRAM-Enhanced Differential Threshold Logic Gates That Are Robust For Low Voltage Operation
All digital circuits use sequences of logic gates that implement Boolean functions to store and transmit binary information. Threshold logic gates receive multiple input signals and produce a single output if the number of signals is below a hardwired threshold value, and can therefore process any Boolean function that might otherwise require multiple...
Published: 2/23/2023   |   Inventor(s): Sarma Vrudhula, Jinghua Yang, Niranjan Kulkarni, Shimeng Yu
Keywords(s): Materials and Electronics
Category(s): Semiconductor Devices
A Robust Asynchronous Scan Chain and Scanning Mechanism for Testing of Digital VLSI Circuits
Very-large-scale-integration (VLSI) is a process of creating massive integrated circuits which enables design of all integrated circuit (IC) components onto a single chip. Thousands of transistors are combined onto a single chip, necessitating highly efficient data scanning in and out of each circuit. Typically the scan-in and scan-out operations are...
Published: 5/22/2024   |   Inventor(s): Sarma Vrudhula, Niranjan Kulkarni
Keywords(s): Materials and Electronics
Category(s): Applied Technologies, Computing & Information Technology, Physical Science, Physics, Wireless & Networking, Semiconductors, Materials & Processes
Clock Skewing Strategy to Minimize Dynamic Power and Eliminate Hold Violations in ASIC Circuits
In digital systems, the difference in the arrival times at two registers is referred to as the clock skew between those registers. Clock skewing is a widely used optimization technique in conventional application-specific integrated circuit (ASIC) designs and typically implemented by introducing buffers to ensure clocking of components happens in the...
Published: 1/24/2024   |   Inventor(s): Sarma Vrudhula, Niranjan Kulkarni, Aykut Dengi
Keywords(s): Circuits, Integrated Circuits, Materials and Electronics
Category(s): Applied Technologies, Computing & Information Technology, Physical Science, Semiconductor Devices
1 2