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TULIP: ASIC Accelerator for QNN with Variable Precision and Tunable Energy-Efficiency
Background
Deep neural networks (DNNs) have been used in many different applications in recent years for pattern recognition and data mining, and are widely considered to be the dominant algorithmic framework in machine learning. However, DNNs are computationally and energetically intensive algorithms that perform billions of floating-point operations...
Published: 2/13/2025
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Inventor(s): Sarma Vrudhula, Ankit Wagle, Gian Singh
Keywords(s):
Category(s): Physical Science, Semiconductor Devices, Artificial Intelligence/Machine Learning
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In-Memory Hardware-Software Co-design for Image Processing
A substantial part of high energy consumption (> 60%) and large latency (> 90%) of conventional von-Neumann architectures can be attributed to the unavoidable data movement between the processor and main memory (DRAM). This is perhaps the major limiting factor for big data and machine learning applications whose usage is permeating into practically...
Published: 2/13/2025
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Inventor(s): Ayushi Dube, Ankit Wagle, Gian Singh, Sarma Vrudhula
Keywords(s): Algorithm Development, Computing Architecture, Imaging, Machine Learning, Performance Optimization, PS-Computing and Information Technology, Resource Management
Category(s): Computing & Information Technology, Imaging, Physical Science
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Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking
Synchronous logic remains the dominant design paradigm of digital systems such as Application Specific Integrated Circuits (ASICs). The conventional design of sequential circuit networks is based on the assumption that every register receives the clock signal at the same time. However, guaranteeing the simultaneity of clock arrival times in practice...
Published: 2/13/2025
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Inventor(s): Sarma Vrudhula, Ankit Wagle
Keywords(s): Circuits, Computing Architecture, Electronics, Integrated Circuits, PS-Applied Technologies, PS-Semiconductor Devices
Category(s): Applied Technologies, Physical Science, Semiconductor Devices
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FPGAs with Reconfigurable Threshold Logic Gates for Improved Performance, Power, and Area
Invention Description
Implementation of lookup tables (LUTs) in a field-programmable gate array (FPGA) comes at the heavy cost of area, power, and performance. Researchers at Arizona State University have developed an alternative FPGA tile structure that consists of three traditional LUTs combined with a new reconfigurable threshold logic cell (TLC)....
Published: 2/13/2025
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Inventor(s): Sarma Vrudhula, Ankit Wagle
Keywords(s):
Category(s): Physical Science, Computing & Information Technology, Semiconductor Devices, Semiconductors, Materials & Processes
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