Search Results - krishnendu+chakrabarty

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TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption
Invention Description Silent data corruptions (SDCs) are particularly difficult to detect because they produce incorrect computational results without generating warnings or system errors. A primary cause of SDCs is voltage droop, a transient reduction in supply voltage that can induce timing violations along critical signal paths. Conventional testing...
Published: 7/21/2026   |   Updated: 7/21/2026   |   Inventor(s): Eduardo Ortega, Krishnendu Chakrabarty, Farshad Firouzi, Deepesh Sahoo
Keywords(s):  
Category(s): Physical Science
LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
Invention Description As semiconductor devices continue to increase in complexity, large-scale computing systems face growing risks of silent data corruptions (SDCs), which produce incorrect computational results without triggering conventional error detection mechanisms. Traditional post-manufacturing testing approaches are often costly, inefficient,...
Published: 7/21/2026   |   Updated: 7/21/2026   |   Inventor(s): Peter Domanski, Krishnendu Chakrabarty, Farshad Firouzi, Deepesh Sahoo, Eduardo Ortega
Keywords(s):  
Category(s): Physical Science
OCTANE: On Chip Telemetry-based Anomaly Notification Engine
Invention Description Integrating hardware into safety- and mission-critical systems has sparked strong demand for combined edge and cloud solutions. This ecosystem helps extend product lifespan while maintaining service quality, driven largely by the Silicon Lifecycle Management (SLM) framework. Silicon Lifecycle Management (SLM) ensures hardware...
Published: 7/8/2026   |   Updated: 7/8/2026   |   Inventor(s): Eduardo Ortega, Krishnendu Chakrabarty
Keywords(s):  
Category(s): Computing & Information Technology, Microelectronics, Semiconductor Devices, Semiconductors, Materials & Processes, Intelligence & Security
SMART: Scalable and Modular Architecture for Routing-Aware Testing of FOWLP
Invention Description Fan-out wafer-level packaging (FOWLP) is an advanced packaging technology that connects multiple chiplets using copper (Cu) pillars and redistribution layers (RDLs). As chiplet-based designs become more complex, they require multi-layer RDLs, which are more prone to defects such as opens, shorts, coupling, and electromigration...
Published: 7/6/2026   |   Updated: 7/6/2026   |   Inventor(s): Dhruv Thapar, Partho Bhoumik, Krishnendu Chakrabarty
Keywords(s):  
Category(s): Microelectronics, Physical Science, Semiconductor Devices, Semiconductors, Materials & Processes
PRISM: Priority-first Repair with Intelligent Spare Mapping
Invention Description As the semiconductor industry transitions from monolithic dies to chiplet-based architectures, interconnect density has increased dramatically, making copper pillars and redistribution layers more susceptible to defects such as voids, delamination, and bridging shorts. Conventional repair approaches, including those defined by...
Published: 7/6/2026   |   Updated: 7/6/2026   |   Inventor(s): Partho Bhoumik, Krishnendu Chakrabarty
Keywords(s):  
Category(s): Physical Science, Semiconductors, Materials & Processes, Semiconductor Devices, Microelectronics
Detection of Stealthy Bitstreams in Cloud FPGAs using Graph Convolutional Networks
Background A field-programmable gate array (FPGA) is a reprogrammable integrated circuit (IC) that can be configured for many different uses. FPGAs are essentially chips that can configured to perform specific tasks after they are manufactured. A multi-tenant FPGA is one that is designed to be shared by multiple, potentially independent, users or “tenants”....
Published: 2/26/2026   |   Updated: 5/21/2025   |   Inventor(s): Jayeeta Chaudhuri, Krishnendu Chakrabarty
Keywords(s):  
Category(s): Physical Science, Intelligence & Security, Artificial Intelligence/Machine Learning, Wireless & Networking