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SMART: Scalable and Modular Architecture for Routing-Aware Testing of FOWLP
Invention Description Fan-out wafer-level packaging (FOWLP) is an advanced packaging technology that connects multiple chiplets using copper (Cu) pillars and redistribution layers (RDLs). As chiplet-based designs become more complex, they require multi-layer RDLs, which are more prone to defects such as opens, shorts, coupling, and electromigration...
Published: 7/6/2026   |   Updated: 7/6/2026   |   Inventor(s): Dhruv Thapar, Partho Bhoumik, Krishnendu Chakrabarty
Keywords(s):  
Category(s): Microelectronics, Physical Science, Semiconductor Devices, Semiconductors, Materials & Processes