Search Results - electrical+%3e+electronics+%26+semiconductors+%3e+waferscale+computing

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A Selenium Buffer Method for Making Van Der Waals Contact on CDTE Wafers With High Surface Roughness (Case No. 2025-173)
Summary: UCLA researchers in the Department of Chemistry & Biochemistry have developed a novel method for implementation of Van der Waals contact on commercial CdTe wafers for improved photovoltaic and solar panel production. Background: Cadmium Telluride (CdTe) is a common absorber used for thin-film optoelectronics and photovoltaics, including...
Published: 1/28/2026   |   Inventor(s): Yu Huang, Xiangfeng Duan, Bangyao Hu
Keywords(s):  
Category(s): Electrical, Electrical > Electronics & Semiconductors, Electrical > Electronics & Semiconductors > Waferscale Computing, Chemical, Chemical > Chemical Processing & Manufacturing, Chemical > Instrumentation & Analysis, Electrical > Sensors, Energy & Environment, Energy & Environment > Energy Efficiency, Energy & Environment > Energy Generation, Materials, Materials > Semiconducting Materials
A High Throughput Thermal Compression Bonding Scheme for Interposer and Wafer-Scale Advanced Packaging Constructs (Case No. 2023-144)
Summary: UCLA researchers in the Department of Electrical and Computer and Engineering have introduced a scalable and rapid bonding method for dielet assembly on advanced packaging constructs, achieving a remarkable throughput of over 1100 units-per-hour, or 10-fold higher than the conventional assembly method. Background: In semiconductor packaging,...
Published: 10/20/2025   |   Inventor(s): Subramanian Iyer, Krutikesh Sahoo, Haoxiang Ren
Keywords(s): advanced packaging, advanced packaging constructs, dielet assembly, dielet bonding, Electronic Packaging, electronics packaging, Fabrication Technologies, face-to-face heterogeneous dielet bonding, heterogeneous integration, heterogenous electronic systems, high throughput, Instrumentation, Interposers, Microelectronics Semiconductor Device Fabrication, Organic Semiconductor, package scaling, Semiconductor, semiconductor chip foundries, Semiconductor Device, Semiconductor Device Fabrication, Semiconductors, thermal compression bonding, wafer-scale, wafer-scale computing, Waferscale Processors
Category(s): Electrical, Electrical > Electronics & Semiconductors, Electrical > Electronics & Semiconductors > Waferscale Computing, Materials, Materials > Semiconducting Materials, Materials > Fabrication Technologies, Electrical > Instrumentation
2017-212 Flexible Fan Out Wafer Processing and Structure: FlexTrate
Flexible Fan Out Wafer Processing And Structure: FlextrateSUMMARYUCLA researchers in the Department of Electrical Engineering have invented a novel biocompatible flexible device fabrication method using fan-out wafer level processing (FOWLP).BACKGROUNDConventional device and substrate technologies require the use of rigid substrates, and it is common...
Published: 7/17/2025   |   Inventor(s): Subramanian Iyer, Takafumi Fukushima, Adeel Bajwa
Keywords(s): Nanosensor
Category(s): Materials > Fabrication Technologies, Electrical > Electronics & Semiconductors > Waferscale Computing