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Search Results - printed+electronics
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Methods of Electrode Configurations and Montages to Achieve Spatial Selectivity of Nerve Stimulation (Case No. 2024-277)
Summary: UCLA researchers in the Department of Bioengineering have developed a novel method for spatially selective electrical nerve stimulation. Background: Peripheral nerve stimulation (PNS) is a common form of treatment for various ailments, such as chronic pain. This approach offers a non-pharmacological and minimally invasive option....
Published: 5/19/2025
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Inventor(s):
Jonathan Brand
,
Wentai Liu
Keywords(s):
Consumer Electronics
,
Digital Electronics
,
Electrode
,
Electrode 3D Printing
,
electrodes
,
Electroencephalography (EEG)
,
Flexible Electronics
,
Machine Learning Pain Management
,
Neuropsychological Test
,
Optoelectronics
,
Organic Electronics
,
Pain Treatment
,
Paint
,
Printed Electronics
,
Psychiatry / Mental Health
,
Psychology
,
Psychotherapy
,
soft electronics
,
Stretchable electrodes
,
tissue-electronic interface
,
wearable electronics
Category(s):
Electrical
,
Electrical > Instrumentation
,
Electrical > Flexible Electronics
,
Medical Devices
,
Medical Devices > Neural Stimulation
,
Therapeutics
,
Therapeutics > Psychiatry And Mental Health
Printed Volatile Memristors for Neuromorphic Computing Hardware
NU 2025-007 INVENTORS Mark Hersam* Shreyash Hadke Vinod Sangwan SHORT DESCRIPTION This technology involves the development of printed volatile memristors designed for neuromorphic computing hardware. These memristors can be printed on flexible substrates, and mimic the complex spiking behavior of biological neurons. BACKGROUND Neuromorphic...
Published: 4/29/2025
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Inventor(s):
Keywords(s):
Printed electronics
Category(s):
Physical Sciences > Materials and Industrial Processes
2021-229 Processes, Equipment and Materials Recipes, and Related Know-How to Perform the Silicon-Interconnect Fabric (Si-IF) Chip-Scale Packaging Technology
Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a novel manufacturing process for Silicone-Interconnect Fabric (Si-IF) that is not only scalable, but also robust as it relies on established processing techniques from CMOS technologies. Background: With the rise of computation-heavy applications, such...
Published: 2/14/2025
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Inventor(s):
Subramanian Iyer
Keywords(s):
Analogue Electronics
,
CMOS
,
Consumer Electronics
,
Digital Electronics
,
Electronic Packaging
,
Electronics & Semiconductors
,
electronics packaging
,
heterogenous electronic systems
,
Integrated Circuit Via (Electronics)
,
Interposers
,
Nanotechnology
,
Power Electronics
,
Printed Circuit Board
,
Printed Electronics
,
Silicon
Category(s):
Electrical
,
Electrical > Electronics & Semiconductors
,
Materials
,
Materials > Nanotechnology
,
Electrical > Electronics & Semiconductors > Memory