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Method for Reducing Process Variation-Induced Threshold Voltage Mismatch in FD-SOI Transistors (Case No. 2025-271)
Reference: UCLA Case No. 2025-271 Please reach out to our office for more information.
Published: 9/12/2025   |   Inventor(s): Subramanian Iyer, Siyun Qiao, Jacklyn Zhu, Samuel Wang
Keywords(s):  
Category(s): Electrical, Electrical > Signal Processing, Electrical > Instrumentation, Electrical > Electronics & Semiconductors, Software & Algorithms, Software & Algorithms > Communication & Networking