A silicon microfluidic chip and fabrication method enable densely integrated vias for parallel droplet generation on a single wafer. Problem: Massively parallel microfluidic chips require large arrays of through-silicon vias to deliver fluid to many devices. Small via footprints are preferred so more features can fit on a single chip. Conventional fabrication approaches can constrain via geometry or scalability when very large via counts are needed. Mechanical instability can also occur when small deep vias are etched directly into the silicon structure. Solution: The technology uses delivery channels, trenches, and vias arranged through a silicon substrate to connect fluid inlets with droplet generators. The trench-based architecture allows smaller vias while helping preserve chip stability. The related fabrication method forms delivery channels, oxide layers, vias, and droplet generators in a controlled sequence. After oxide removal, the vias are placed in fluid communication with the delivery channels to create the operating device. Technology Overview: The chip includes a substrate with first and second surfaces, inlets for continuous and dispersed phase fluids, delivery channels, trenches, vias, droplet generators, and at least one outlet. The trenches extend from the delivery channels toward the droplet generators, and the vias fluidly connect those structures. In claimed and described embodiments, the architecture supports highly parallelized flow-focusing droplet generation on silicon. Demonstrated embodiments include chips with 20,160 droplet generators and more than 50,000 vias on a single 4-inch wafer. Advantages:
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(a) An SEM micrograph of the cross section of the chip. Scale bar 115 µm. (b) The FFGs used in our previous 10k-VLSDI 1.0 chip20. Scale bar 80 µm. (c) FFGs used in this work, VLSDI 2.0, where the device footprint has been scaled down by a factor of two compared to the prior work. Scale bar 80 µm. Intellectual Property:
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Docket #18-8645