Search Results - dynamic+random-access+memory

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Secure Agents for Flexible Clean Rooms and Access Control (Case No. 2026-043)
Summary: UCLA researchers in the Department of Computer Engineering and Mathematics have developed virtual secure agents that enable efficient, privacy-preserving collaborative computation across all standard cloud environments. Background: Data clean rooms are secured environments that allow multiple parties to safely upload and exchange data between...
Published: 10/28/2025   |   Inventor(s): Rafail Ostrovsky, Sam Kumar, Nakul Khambhati, Joonwon Lee, Gary Song
Keywords(s): Cloud Computing, Computer Security, Condition monitoring, Data Analytics, data security, Data Structure, Database management/data entry, Dynamic Random-Access Memory, multiparty network, scalable communication, security, Security and defense
Category(s): Software & Algorithms, Software & Algorithms > Communication & Networking, Software & Algorithms > Data Analytics, Software & Algorithms > Security & Privacy
Charge Trap Transistors - Subramanian Iyer
Background: Due to their chemical makeup and heat generation, devices such as high-k/metal gate (HKMG) CMOS often accumulate charges can lead to variation in integrated circuits. Charge Trap Transistors (CTT's) utilize accumulating charge in semiconducting devices as embedded non-volatile memory (eNVM). The introduction of CTT's can prove an...
Published: 7/17/2025   |   Inventor(s): Subramanian Iyer
Keywords(s): Charge Carrier, CMOS, Dynamic Random-Access Memory, Electrical, Electrical Engineering, Electrical Load, Electrical Resistance And Conductance, Logic Gate, Magnetoresistive Random-Access Memory, Medical Device, Memory, Power Electronics, Power Transmission, Programmable Logic Device, Random-Access Memory, Resistive Random-Access Memory, Semiconductor Device, Semiconductor Device Fabrication, Static Random-Access Memory, Transistor
Category(s): Electrical, Electrical > Electronics & Semiconductors > Memory, Electrical > Electronics & Semiconductors
2021-212 Configurable Memory Pool System
Summary: UCLA researchers in the Department of Electrical and Computer Engineering have developed a node processing architecture that allows memory pool to be scalable and allows the integration of heterogeneous technologies downstream. Background: Modern electronic applications require high memory capacity and bandwidth. However, many of these applications...
Published: 7/17/2025   |   Inventor(s): Puneet Gupta, Saptadeep Pal, Matthew Tomei, Rakesh Kumar
Keywords(s): Bandwidth (Computing), Dynamic Random-Access Memory, Electrical Engineering, Flash Memory, Latency (Engineering), Magnetoresistive Random-Access Memory, Random-Access Memory, Static Random-Access Memory
Category(s): Electrical, Electrical > Electronics & Semiconductors > Circuits, Electrical > Electronics & Semiconductors