NU 2016-047
Inventors
Mark Hersam*
Alan Sahakian
Michael Geier
Joseph Friedman
Short Description
Novel cascaded ambipolar logic family structures for higher efficiency computing
Abstract
Increasing computer hardware efficiency for next generation computing requires robust scaling of Si complementary metal oxide semiconductor (CMOS) field effect transistor (FET) logic circuits. However, physical limits of CMOS scaling necessitate improvements of internal hardware like the switching devices and logic structures. Single-walled carbon nanotubes (CNTs) are particularly attractive FETs due to their efficiency and ability operate at higher voltage ranges. The majority of efforts have been applied to the use of CNT FETs as unipolar electrical switches with one addressable gate. The use of two independently addressable gates for ambipolar FETs has been proposed, but resulting structures have been highly complex, less efficient, and expensive to fabricate. Northwestern engineers have developed a novel cascaded logic family that exploits ambipolar FETs in a different way. They propose the use of a common back gate that can be shared by complementary pairs of ambipolar FETs, decreasing the device count by 50%-75%. This adjustment leads to significant computing improvements related to power and speed, providing the ability to perform complex computations with fewer devices and logic stages. The design and fabrication are also simplified as bottom and top gates can also be shared by complementary pairs of ambipolar FETs. The exceptional features of this logic family make it a highly competitive contender to replace CMOS in the next generation of computing.
Applications
Advantages
IP Status
A US provisional patent application has been filed.