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Reinforcement Learning for Fault-tolerant Energy-efficient NoC Design
Researchers at GW have developed a novel, cost-effective, energy-efficient computer architecture design based on reinforcement learning (RL) for use in various computing applications. The disclosed design has better fault-tolerance, reliability, network latency than existing solutions. The disclosed computer architecture design can include an Error...
Published: 7/30/2024   |   Inventor(s): Ahmed Louri, Ke Wang
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Cybersecurity, Technology Classifications > Computers Electronics & Software > Processing Chips
Compact ultra-low power 2x2 Photonic Switch on Silicon
Researchers at George Washington University recently invented an optical switching technology for future photonics network-on-chip (NOC). This invention enables compact, cost-effective two orders of magnitude increases in bandwidth and dramatically more energy-efficient communication between CPU’s compared to traditional electrical interconnects....
Published: 7/30/2024   |   Inventor(s): Volker Sorger, Chenran Ye, Ke Liu
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Sensors, Technology Classifications > Computers Electronics & Software > Computing Architecture
SAM: Spintronic Approximate Memory
In the ever-evolving landscape of artificial intelligence (AI), achieving power efficiency without sacrificing accuracy has been a perennial challenge. Traditional methods, such as low supply voltage SRAM and low refresh rate DRAM, have aimed to reduce power consumption but have fallen short due to their lack of bitwise control over memory accuracy....
Published: 7/30/2024   |   Inventor(s): Abdolah Amirany, Tarek El-Ghazawi, Hamidreza Imani Porshokouh
Keywords(s):  
Category(s): Technology Classifications, Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips, Technology Classifications > Computers Electronics & Software > Databases
SPACX: A Hardware and Algorithm Co-Optimized Photonic Deep Neural Network Computing Architecture
SPACX- A silicon-based Photonic accelerator for DNN Chiplets architecture The continuous increase in size and complexity of deep neural network (DNN) models leads to rapidly increasing demand for computing capacity which has outpaced the scaling capability of conventional monolithic chips. Chiplet-based DNN accelerators have emerged as a promising...
Published: 7/30/2024   |   Inventor(s): Yuan Li, Ahmed Louri
Keywords(s):  
Category(s): Technology Classifications, Technology Classifications > Computers Electronics & Software, Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Processing Chips, Technology Classifications > Computers Electronics & Software > Computing Architecture
Symmetry-Detecting Spiking Artificial Neural Network
Researchers at GW have developed a novel and efficient solution to detect symmetry lines and points within multidimensional spatial data that could be utilized in data processing and robotics. The solution can take the form of one or more artificial neural networks that can be configured to efficiently detect symmetry lines and points within multidimensional...
Published: 7/30/2024   |   Inventor(s): Jonathan George, Volker Sorger
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Cloud Computing, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Robotics, Technology Classifications > Computers Electronics & Software > Artificial Intelligence
Hybrid Photonic Plasmonic Non-blocking Wide Spectrum WDM On-chip Router
Researchers at GW have developed a novel hybrid photonic plasmonic non-blocking wide spectrum WDM On-chip Router. The disclosed invention is highly energy efficient. For example, the design could be used as optical routers in optical networks with non-blocking routing strategy, femtojoule energy efficiency and ultra-high operating speed. Further, through...
Published: 7/30/2024   |   Inventor(s): Shuai Sun, Volker Sorger, Tarek El-Ghazawi, Vikram Narayana
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Sensors, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Cloud Computing, Technology Classifications > Computers Electronics & Software > Databases, Technology Classifications > Computers Electronics & Software > Processing Chips
Functional Casing in Erasure Coded Storage
Researchers at GW have developed a novel, cost-effective, energy-efficient solution, in the field of storage systems, to perform functional casing in erasure coded storage systems. The solution has applications in various computing architecture related products as can be appreciated. For instance, the solution utilizes a novel casing approach in erasure...
Published: 7/30/2024   |   Inventor(s): Yu Xiang, Yih-Farn Chen, Vaneet Aggarwal, Tian Lan
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Databases
EZ-PASS: An Energy & Performance-Efficient Power-gating Router Architecture for Scalable NoCs
Researchers at GW have developed a novel router architecture that is capable of being implemented on various networking applications. The router architecture can be used for high-performance communication which only consumes little energy while still providing high speed. This architecture has a greater impact on applying power-gating for various interconnects...
Published: 7/30/2024   |   Inventor(s): Ahmed Louri, Hao Zheng
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
A Hardware-based Cyber-deception Framework to Combat Malware
Researchers at GW have developed a hardware-based cyber-deception framework that can effectively combat malware directed to attacking computer systems. In particular, the framework works deceptively and transparently, to modify the underlying malware during program runtime and strategically deflects the malware from accessing sensitive information associated...
Published: 7/30/2024   |   Inventor(s): Guru Venkataramani, Preet Derasari, Kailash Gogineni
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Cybersecurity
Reuse-trap: Re-purposing Cache Reuse Distance to Defend against Side Channel Leakage
Researchers at GW have developed a novel solution that serves to capture the activity of an adversary in a cache timing channel. The novel solution can detect advanced attack variants of cache timing channel which can evade the detection of the existing technology by mimicking activities of benign applications and obfuscating mutual eviction patterns....
Published: 7/30/2024   |   Inventor(s): Guru Venkataramani, Milos Doroslovacki, Hongyu Fang
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Cloud Computing, Technology Classifications > Computers Electronics & Software > Cybersecurity, Technology Classifications > Computers Electronics & Software > Computing Architecture
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