Search Results - ahmed+louri

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A Versatile Accelerator Design for Multiple Deep Neural Network Applications
Deep Neural Networks (DNNs) have become integral to numerous applications, from image recognition to video processing, touching almost every aspect of modern life. The expansion of DNN applications has led to increasing demands on underlying hardware architectures, particularly in terms of memory bandwidth and communication requirements. Despite numerous...
Published: 10/14/2024   |   Inventor(s): Jiaqi Yang, Hao Zheng, Ahmed Louri
Keywords(s):  
Category(s): Technology Classifications, Technology Classifications > Computers Electronics & Software, Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
Reinforcement Learning for Fault-tolerant Energy-efficient NoC Design
Researchers at GW have developed a novel, cost-effective, energy-efficient computer architecture design based on reinforcement learning (RL) for use in various computing applications. The disclosed design has better fault-tolerance, reliability, network latency than existing solutions. The disclosed computer architecture design can include an Error...
Published: 7/30/2024   |   Inventor(s): Ahmed Louri, Ke Wang
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Cybersecurity, Technology Classifications > Computers Electronics & Software > Processing Chips
SPACX: A Hardware and Algorithm Co-Optimized Photonic Deep Neural Network Computing Architecture
SPACX- A silicon-based Photonic accelerator for DNN Chiplets architecture The continuous increase in size and complexity of deep neural network (DNN) models leads to rapidly increasing demand for computing capacity which has outpaced the scaling capability of conventional monolithic chips. Chiplet-based DNN accelerators have emerged as a promising...
Published: 7/30/2024   |   Inventor(s): Yuan Li, Ahmed Louri
Keywords(s):  
Category(s): Technology Classifications, Technology Classifications > Computers Electronics & Software, Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Processing Chips, Technology Classifications > Computers Electronics & Software > Computing Architecture
EZ-PASS: An Energy & Performance-Efficient Power-gating Router Architecture for Scalable NoCs
Researchers at GW have developed a novel router architecture that is capable of being implemented on various networking applications. The router architecture can be used for high-performance communication which only consumes little energy while still providing high speed. This architecture has a greater impact on applying power-gating for various interconnects...
Published: 7/30/2024   |   Inventor(s): Ahmed Louri, Hao Zheng
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
An Approximate Communication Framework for Network-on-chips
Reasearchers at GWU have developed an approximate communication framework for network-on-chips (NoCs), which significantly reduces the latency and power consumption of on-chip data movement. The invented framework leverages the fact that big data applications (e.g., recognition, mining, and synthesis) can tolerate modest error and transfers data with...
Published: 7/30/2024   |   Inventor(s): Ahmed Louri, Yuechen Chen
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
Network Design for Chiplet-based Manycore Architecture
Researchers at The George Washington University are developing a flexible interconnection network design, called Adapt-Net, for chiplet-based manycore architectures. The goal of Adapt-Net is to support the concurrent communication of diverse applications running at the same time, improving the energy-efficiency and performance of the manycore architecture....
Published: 7/30/2024   |   Inventor(s): Hao Zheng, Ke Wang, Ahmed Louri
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software, Technology Classifications > Computers Electronics & Software > Computing Architecture
A Flexible and Energy-Efficient Accelerator for Graph Convolutional Neural Networks
Researchers at GW have invented a flexible and energy-efficient accelerator for graph convolutional neural networks (GCN). First, the novel accelerator design disclosed shows highly enhanced performance in comparison to existing accelerators. For example, the accelerator is capable of simultaneously improving resource utilization and data movement in...
Published: 7/30/2024   |   Inventor(s): Ahmed Louri, Jiajun Li
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Computing Architecture
An Algorithm-Hardware Co-design Method for Convolutional Neural Networks
Researchers at GW have developed an algorithm-hardware co-design framework for Convolutional Neural Networks (CNN) directed towards mitigating the effects of computational irregularities in existing models. The framework disclosed allows for a reduced model size as to the associated system. For example, the algorithm disclosed utilizes centrosymmetric...
Published: 7/30/2024   |   Inventor(s): Jiajun Li, Ahmed Louri
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Artificial Intelligence
Learning-Based High-Performance, Energy-Efficient, and Secure Interconnection Design Framework
Researchers at the George Washington University have invented a novel network-on-chip framework, named TSA-NoC, which significantly improves on-chip security. The invented framework also minimizes the latency and cost of security techniques for simultaneously improving system-level performance and power. As the market for parallel computing is growing...
Published: 7/30/2024   |   Inventor(s): Ke Wang, Hao Zheng, Ahmed Louri
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
A Fault Tolerant and Power Efficient Network-on-Chip Architecture using Quad-Function Channel (QFC) Buffers
QORE is a fault tolerant Different Network on Chip (NoCs) that seeks to reduce power consumption and improve performance of NoCs while mitigating errors caused by faults. Through a new type of data buffer and connecting multiple processing cores QORE has the ability to reduce power and avoid faults. Background: With electrical components shrinking...
Published: 8/1/2024   |   Inventor(s): Avinash Kodi, Dominic Ditomaso, Ahmed Louri
Keywords(s):  
Category(s): Technology Classifications > Engineering & Physical Sciences > Communications & Networking > Networking, Technology Classifications > Engineering & Physical Sciences > Electronics > Computer Hardware
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