Search Results - tarek+el-ghazawi

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A Resilient, Adaptive, Multi-Context Switching, Energy-Efficient Spintronic FPGA (RAMSES-FPGA)
Static random-access memories (SRAM) based FPGAs are susceptible to Single Event Upsets (SEUs). SEUs are transient faults caused by high-energy particles striking the semiconductor material which result in unintended changes in the stored data. This vulnerability is a significant concern specifically in environments with high levels of radiation, such...
Published: 7/28/2025   |   Inventor(s): Abdolah Amirany, Samuel Farid, Hamidreza Imani Porshokouh, Tarek El-Ghazawi
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software, Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
ESSRA: An Efficient Spintronic Stochastic Reconfigurable Architecture
Recent research in Stochastic Computing (SC) is focused on practical methods for bitstream generation, optimizing logic operations for stochastic data, and developing architectures that natively support SC. This approach has proven particularly promising in simplifying and accelerating complex computations in fields such as AI and image processing....
Published: 7/28/2025   |   Inventor(s): Abdolah Amirany, Hamidreza Imani Porshokouh, Samuel Farid, Tarek El-Ghazawi
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips
SAM: Spintronic Approximate Memory
In the ever-evolving landscape of artificial intelligence (AI), achieving power efficiency without sacrificing accuracy has been a perennial challenge. Traditional methods, such as low supply voltage SRAM and low refresh rate DRAM, have aimed to reduce power consumption but have fallen short due to their lack of bitwise control over memory accuracy....
Published: 7/28/2025   |   Inventor(s): Abdolah Amirany, Tarek El-Ghazawi, Hamidreza Imani Porshokouh
Keywords(s):  
Category(s): Technology Classifications, Technology Classifications > Computers Electronics & Software > Artificial Intelligence, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Processing Chips, Technology Classifications > Computers Electronics & Software > Databases
Two Optical Convolutional Neural Network Accelerator
In today's AI revolution, Neural Networks (NNs) have taken center stage, driving remarkable progress in artificial intelligence over the past decade. However, existing technologies like FPGA and GPU implementations, though widely used for accelerating Convolutional Neural Networks (CNNs) face significant limitations in terms of speed, energy efficiency,...
Published: 7/28/2025   |   Inventor(s): Armin Mehrabian, Volker Sorger, Tarek El-Ghazawi, Mario Miscuglio
Keywords(s):  
Category(s): Technology Classifications, Technology Classifications > Computers Electronics & Software
Hybrid interconnects for on-chip communication: A solution with low latency and efficient energy consumption
­​​​​​​As computer chip feature size continue to decrease, power consumed due to on-chip communications will dramatically grow. This calls for new techniques which can provide higher bandwidth and data rates than over traditional electrical interconnects. Photonic interconnects can provide higher bandwidth and data rates. However optoelectronic...
Published: 7/28/2025   |   Inventor(s): Shuai Sun, Volker Sorger, Tarek El-Ghazawi, Vikram Narayana, Abdel-Hameed Badawy
Keywords(s):  
Category(s): Technology Classifications > Industrial or Consumer Tech > Energy Infrastructure and Environment, Technology Classifications > Industrial or Consumer Tech > Materials, Technology Classifications > Computers Electronics & Software > Processing Chips
Hybrid Photonic Plasmonic Non-blocking Wide Spectrum WDM On-chip Router
Researchers at GW have developed a novel hybrid photonic plasmonic non-blocking wide spectrum WDM On-chip Router. The disclosed invention is highly energy efficient. For example, the design could be used as optical routers in optical networks with non-blocking routing strategy, femtojoule energy efficiency and ultra-high operating speed. Further, through...
Published: 7/28/2025   |   Inventor(s): Shuai Sun, Volker Sorger, Tarek El-Ghazawi, Vikram Narayana
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Sensors, Technology Classifications > Computers Electronics & Software > Computing Architecture, Technology Classifications > Computers Electronics & Software > Cloud Computing, Technology Classifications > Computers Electronics & Software > Databases, Technology Classifications > Computers Electronics & Software > Processing Chips
Residue Number System Adder and Multiplier based on Integrated Nanophotonics
Researchers at GW have developed a novel, cost-effective, and energy-efficient residue number system (RNS) adder and multiplier that is based on integrated nanophotonics. The disclosed invention utilizes multiplication-accumulation computation (MAC) operations that can use one summand/multiplicand repetitively millions of times. In other words, aspects...
Published: 7/28/2025   |   Inventor(s): Volker Sorger, Tarek El-Ghazawi, Shuai Sun, Jiaxin Peng
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Cloud Computing, Technology Classifications > Computers Electronics & Software > Artificial Intelligence
The Reconfigurable Optical Coprocessor
Researchers at GW have developed a novel, cost-effective, energy-efficient solution having enhanced performance, programmable array of photonic R (and LC) components using nanoplasmonics technology in order to solve systems that can be described through differential equations and converted into electrical analogues. The solution involves computing processes...
Published: 7/28/2025   |   Inventor(s): Volker Sorger, Tarek El-Ghazawi, Shuai Sun, Vikram Narayana, Abdel-Hameed Badawy
Keywords(s):  
Category(s): Technology Classifications > Computers Electronics & Software > Robotics, Technology Classifications > Computers Electronics & Software > Sensors, Technology Classifications > Computers Electronics & Software > Processing Chips