Simplified Process for Fabricating Interdigitated Energy Storage Devices

Researchers at The University of Arizona and the University of California, Irvine, have developed a simplified process to prepare interdigitated energy storage devices (IESD). These are compact, 3-dimensional structures with superior energy densities: projected values are approximately 10,000 times larger than a conventional parallel plate capacitor. IESD's contain high-surface area nano-rods of conducting material, allowing for more energy storage per unit volume than a parallel plate capacitor could ever hope to achieve. IESD's can be fabricated from commercially available nano-porous templates such as polycarbonate and aluminum oxide membranes, or customized nano-porous templates of very high dialectric coefficient.

Applications:

• Pulse power demanding systems
• Small-scale and portable electronics
• Stand-alone sensor network device
• Integrated circuits (IC)

Advantages:

• Large energy storage, but very small physical volume, versus parallel plate capacitors: significantly lesser footprint
• Relatively simple manufacturing process envisaged: ease of scale-up for quality control and management
• Combinations of various membrane and inclusion materials are possible, for flexible device characteristics and performance

Status: issued U.S. Patent #8,385,046