PAGE TITLE
Overview
PAGE SUMMARY
Integrated Circuits (ICs), which serve as the keystone of modern electronic devices, are increasingly vulnerable to third party tampering due to the industry’s increasing reliance on untrusted third-party foundries in the IC design flow. The result is a growing concern of IC reliability and security, with threats that include: IC counterfeiting, intellectual property (IP) theft, IC overproduction, and the insertion of hardware Trojans. To mitigate these threats, researchers have explored the use of logic encryption, however existing methods, such as XOR and look-up table (LUT) based logic encryption suffer drawbacks in high per-gate overheads in power, area and performance. To overcome these deficiencies, a team of Drexel researchers have developed two separate gate level logic encryption techniques aimed at ensuring the reliability and security of ICs in critical applications while achieving markedly lower power, area, and performance overhead. In particular, the team has developed two techniques including: 1) Modifications to standard CMOS cells to include key transistors, and 2) transmission gate logic encryption, which also includes key inputs to the gate. Relative to the best known approach (XOR based implementation of the encrypted AND) both methods yield similar improvements with a power reduction of 43.2%, an estimated area reduction of 19.8%, and a performance increase of 46.9%.
APPLICATIONS
TITLE: Applications
IC Functionality Masking
ADVANTAGES
TITLE:Advantages
Reliable
Low Power Overhead
Reduced Performance Impact
Reduced area overhead
FIGURES: Insert Figure Image Inside Figure Tags within Editor
Figure 1
Figure 1 Caption:
Stack -Based Topology
Figure 2
Figure 2 Caption
Transmission Gate -Based Topology
IP STATUS
Intellectual Property and Development Status
PCT application Pending- PCT/US16/058393
https://patentscope.wipo.int/search/en/detail.jsf?docId=WO2017123305
PUBLICATIONS
References
Pubinfo should be the citation for your publication. Publink is the full url linking to the publication online or a pdf.
Kyle Juretus and Ioannis Savidis. 2016. Reduced Overhead Gate Level Logic Encryption. In Proceedings of the 26th edition on Great Lakes Symposium on VLSI (GLSVLSI '16). ACM, New York, NY, USA, 15-20. DOI=http://dx.doi.org/10.1145/2902961.2902972
http://dl.acm.org/citation.cfm?id=2902972
Multimedia Link
http://ice.ece.drexel.edu
Commercialization Opportunities
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Contact Information
Robert B. McGrath, Ph.D.
Senior Associate Vice Provost
Office of Technology Commercialization
Drexel University
3180 Chestnut Street, Ste. 104
The Left Bank
Philadelphia, PA 19104
Phone: 215-895-0303
Email: RBM26@drexel.edu
For Technical Information:
Ioannis Savidis, PhD
Assistant Professor
Department of Electrical and Computer Engineering
3120-40 Market Street, Bossone 610
Philadelphia, PA 19104-2875
Phone: +1-215-571-4584
Email: isavidis@coe.drexel.edu