Network-on-Chip (NoC) Systems with Wireless Interconnects

 

This is an enabling technology to design energy efficient and high bandwidth multicore architectures with improved thermal profile over conventional wireline.  Evaluation yielded lower latency and energy dissipation compared to a conventional wireline mesh.  Network-on-chip (NoC) or network-on-a-chip is a communication subsystem on an integrated circuit (IC), typically between cores in a system on a chip (SoC).  NoC technology applies networking theory and methods to on-chip communication and brings notable improvements over conventional bus and crossbar interconnections.  NoC improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs.  The millimeter wave small world wireless NoC is an enabling interconnect architecture to design high performance and low power multi-core chips.  A high level of parallelism is achieved, because all links in the NoC can operate simultaneously on different data packets.

 

Since most of the these NoC technologies usually have irregular topology, it is important to have a suitable design that is going to solve dead-lock free routing mechanisms.  This technology calculates parameters like latency, energy dissipation and thermal profiles of NoC architectures by incorporating irregular network routing strategies.

 

 

1.       Integrated circuits can serve multiple concurrent computational requests.

2.       Avoid dead-lock problem, with lower latency and energy dissipation.

3.       Efficient results when compared to traditional methods.

 

 

Issued Patent, US 9,876,708