Modern integrated circuits often need on-chip light sources for optical interconnects, but traditional off-chip lasers suffer from drawbacks such as large footprint, high energy consumption, slower modulation speeds, and inefficient coupling losses to on-chip waveguides. Existing approaches rely on III-V semiconductor lasers that are either separately packaged or bonded onto silicon, which complicates manufacturing and integration. These systems struggle with scalability, compatibility with CMOS processes, and excessive parasitics, limiting their effectiveness in high-bandwidth, power-sensitive environments.
Researchers at GW have developed a novel plasmonic mode III‑V nano‑laser architecture directly integrated onto a CMOS substrate. At its core is a 250 × 250 nm square cavity containing III‑V quantum wells bonded onto silicon via oxide‑wafer transfer. A plasmonic metal electrode excites surface plasmons in this nano‑cavity, generating coherent light that efficiently couples into adjacent or in‑line waveguides. This on‑chip plasmonic laser achieves high modulation speed, reduced footprint, and significantly lower energy loss up to 10–15 dB less, while being fully compatible with standard CMOS fabrication.
Figure. Shows a perspective view of a nano-laser and two cross-section views taken as section planes A-A and B-B showing temperature profiles of the nano-laser
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