PAGE TITLE
Overview
PAGE SUMMARY
A clock mesh network has been the preferred clock network structure for high-end microprocessor design because of its tolerance to variations. The variation tolerance is achieved by placing the redundant mesh grid wires near the sink registers, but at the cost of power dissipation. To overcome the limitations of existing clock mesh networks, a team of Drexel researchers has developed a clock mesh network synthesis method which enables clock gating on the local sub-trees of the clock mesh network in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path of the design area. The method encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. With gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The method has modes of low power and high performance to serve different design purposes.
APPLICATIONS
TITLE: Applications
High End Microprocessor Designs
ADVANTAGES
TITLE:Advantages
Lower Power Consumption - power consumption of the clock mesh network is reduced compared to previous clock mesh design methods due to the combination of clock gating, steiner tree connection and the register clustering.
Timing Closure - the non-negative timing slack of the circuit is preserved after the incremental register placement. The slack decrease tolerance is designer-specified.
Register Placement Optimization - the incremental register placement is performed in local areas only, which preserves the placement optimization for timing and routing.
FIGURES: Insert Figure Image Inside Figure Tags within Editor
Figure 1
IP STATUS
Intellectual Property and Development Status
United States Patent Pending- 8,704,577
http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8704577.PN.&OS=PN/8704577&RS=PN/8704577
PUBLICATIONS
References
Pubinfo should be the citation for your publication. Publink is the full url linking to the publication online or a pdf.
J. Lu, X. Mao and B. Taskin, "Clock Mesh Synthesis with Gated Local Trees and Activity Driven Register Clustering", IEEE/ACM International Conference on Compute on Computer-Aided Design (ICCAD), November 2012, pp. 691--697.
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=6386749
Commercialization Opportunities
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Contact Information
Robert B. McGrath, Ph.D.
Senior Associate Vice Provost
Office of Technology Commercialization
Drexel University
3180 Chestnut Street, Ste. 104
The Left Bank
Philadelphia, PA 19104
Phone: 215-895-0303
Email: RBM26@Drexel.edu
For Technical Information:
Baris Taskin, Ph.D.
Associate Professor
Department of Electrical and Computer Engineering
3141 Chestnut Street
Philadelphia, PA 19104-2875
Phone: (215) 895-5972
E-mail: taskin@coe.drexel.edu
Web: http://vlsi.ece.drexel.edu