Fault- and Variation-Tolerant Energy- and Area-Efficient Links for Network-on-Chips (NoCs)

Researchers in the University of Arizona's Department of Electrical and Computer Engineering developed an enhancement to the Inter-Router Dual-Function Energy and Area Efficient Links (iDEAL) design for Network-on-Chips (NoC). This development adds dynamic error correction and fault-tolerance capability to the iDEAL design scheme and overcomes many disadvantages present in traditional error-correction schemes while achieving low-latency and low power consumption.
 

Background:

This enhancement to the Inter-Router Dual-Function Energy and Area Efficient Links (iDEAL) design for Network-on-Chips (NoC) adds dynamic error correction and fault-tolerance capability to the iDEAL design. This enhancement maintains the advantages of the iDEAL design, such as low power consumption without degraded performance, while improving signal integrity and reliability. By deploying circuit-level enhancements to the original iDEAL design, error recovery is achieved even when downstream data propagation congestion exists. Further improvements assist to avoid data flow stalls and improve throughput while employing a dynamic boosting scheme that further improves data-flow speed. These techniques provide robust error recovery and improve the performance of the iDEAL and other NoC architectures.

Advantages:

• Dynamic error-correction and fault-tolerance while maintaining the high performance and low power consumption of the iDEAL chip design
• Design is adaptable to existing chip architectures

Applications:

• Chips utilizing the iDEAL NoC design
• Chips utilizing existing NoC and SoC architectures