When transmitting and receiving electromagnetic signals, there is a need to match the frequencies and the phases of both a received signal and a locally generated signal. In terms of signal to noise ratio (SNR), the alignment of the phases gives the best results for retrieving any data that is modulated on the received signal. Better SNR yields higher accuracy results for applications such as wireless communications, radar, imaging, and photonics.
A phase lock loop (PLL) is an electronic circuit and control system that includes a voltage or voltage-driven oscillator that constantly adjusts to match the frequency of an input signal. Standard PLLs use a Phase-Frequency Detector (PFD) made of digital circuits and are limited to input signals with frequencies of less than 1 GHz. These PLLs have two major drawbacks: (1) closed loop bandwidth is limited to less than one tenth of the input reference frequency which would limit the bandwidth of the PLL and (2) requires frequency divider circuits to bring its input signals down to the frequency of the reference with frequencies below 500 MHz. There is a need for a PLL architecture that can effectively operate (i.e., perform frequency locking) on signals of high frequencies.
Researchers at Arizona State University have developed a fast-tracking phase lock loop (PLL) for phase and frequency detection and synchronization. A frequency lock loop architecture is used for a PLL that can lock the phase of a local oscillator to an input reference signal of arbitrarily high frequency, even if the local oscillator and the input reference signal frequencies are originally very far apart (e.g., several GHz).
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