PAGE TITLE
Enhanced Circuit Security Through Hidden State Transitions
PAGE SUMMARY
Because of the globalization of manufacturing process, integrated circuits (ICs) have become increasingly vulnerable to Counterfeiting and Intellectual Property theft. The consequences can be dramatic when critical systems begin to fail due to the use of counterfeit or low-quality components. Moreover legitimate electronics companies miss out on about $100 billion of global revenue every year because of counterfeiting and IP theft. Unauthorized IP copies start from reverse engineering the given chip and till day logic obfuscation is one of the most promising approaches to protect from IP theft. The designer adds additional inputs and modules to the design to hide the correct functionality, while a locking key (unknown to the foundry and written later in a tamper-proof memory) is used to activate the IC. However, attacks like SAT(Satisfiability attack) that iteratively solve for correct keys, circumvent the security provided by logic encryption and, therefore, requires the development of novel measures to defend against the wide variety of threats facing ICs.
Addressing these concerns researchers at Drexel have now developed a novel logic locking technique that significantly increases the output corruptibility (i.e., produce more incorrect outputs for more input patterns) given an incorrect key, and prevents from effective key- learning attacks. The technique uses the state space of an integrated circuit (IC) to increase security, specifically timing path dependencies and coupling capacitance are utilized to create hidden state transitions that are not observable after netlist extraction. The technique offers zero performance overhead and a significant reduction in both area and power overheads compared to existing techniques. In addition to the hidden state transitions technique, Drexel has also developed a novel algorithm that efficiently selects locations to insert logic encryption in a design leading to much lower run-times than current algorithms. This allows for faster insertion, while still achieving increased security, paving the way for an efficient way to transform a non-secure IC design into one that can withstand IP theft and reverse engineering.
APPLICATIONS
TITLE: Applications
Security against Intellectual Property theft
Prevention of IC Counterfeiting and Overproduction
ADVANTAGES
TITLE:Advantages
Provides a low cost means of securing an IC.
Offers zero performance overhead and significant reduction in both area and power overheads.
Increases the decryption time for attacks exponentially compared to existing techniques.
IP STATUS
Intellectual Property and Development Status
Provisional Patent Filed
PUBLICATIONS
References
K. Juretus and I. Savidis, "Time Domain Sequential Locking for Increased Security," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, 2018, pp. 1-5.
https://ieeexplore.ieee.org/abstract/document/8351412
K. Juretus and I. Savidis, "Enhanced Circuit Security Through Hidden State Transitions,” 2018.
http://ece.drexel.edu/savidis/publications/GOMAC_2018a.pdf
K. Juretus, I. Savidis, "Importance of Multi-parameter SAT Attack Exploration for Integrated Circuit Security" 2018.
http://ece.drexel.edu/savidis/publications/APCCAS_2018-208.pdf
Contact Information
Harshith Reddy
Licensing Manager
215-571-4290
harshith@drexel.edu