This image-processing algorithm segments the structural elements of integrated circuits in scanning electron microscopy (SEM) images to enable reverse engineering or failure analysis. The increasing complexity of advanced integrated circuit (IC) chips has rendered optical imaging obsolete for efficient reverse engineering. Computer vision algorithms now expedite reverse engineering of present-day integrated chips by processing higher-resolution scanning electron microscopy images of the densely packed chips in order to automate structural component segmentation. However, available segmentation algorithms only work on higher-quality scanning electron microscopy images, which take a very long time to process and require human interaction to optimize image parameters.
Researchers at the University of Florida have developed an algorithm that analyzes a low-quality scanning electron microscopy image of an integrated circuit and automatically segments the image into structural elements for reverse engineering. The algorithm enables faster integrated circuit imaging and eliminates any need for human interaction, increasing efficiency in the reverse engineering process.
Computer vision algorithm that automatically segments the structural elements of integrated circuits in scanning electron microscopy images to aid reverse engineering, failure analysis, debugging, hardware security, and intellectual property protection
This algorithm applies histogram-based auto segmentation to the integrated circuit (IC) structures present in scanning electron microscopy (SEM) images acquired under low magnification and/or having poor qualities. The algorithm sets the scanning electron microscopy image through a series of stages in which it extracts the histogram of the image, corrects it, and segments the histogram based on its number of peaks. The algorithm does not try to model noise sources and does not require parameter fine-tuning. The segmentation algorithm relies on the working principles of scanning electron microscopy imaging to produce a high-contrast integrated circuit image suitable for reverse engineering or failure analysis. This greatly simplifies the traditionally lengthy and expensive integrated circuit reverse engineering workflow.