Integrated circuits form the backbone of modern electronics, yet their globally distributed design and manufacturing processes leave them dangerously exposed. Hardware trojans, malicious modifications inserted by adversaries, can silently leak sensitive data, degrade performance, or trigger catastrophic failures. Traditional detection methods are manual, error prone, and lack the scalability needed for today's complex circuits, often failing entirely when a trusted reference design is unavailable.
This technology takes a graph-based approach to hardware trojan detection, representing circuit designs as directed acyclic graphs and analyzing switching activity across time windows to identify rare, non-toggling paths that stealthy triggers exploit. Unlike conventional solutions that examine paths individually and struggle with manufacturing variations, this system evaluates multiple paths simultaneously without requiring a golden reference design. The result is a scalable, automated, and variation resilient tool that delivers strong detection rates across both pre and post silicon analysis.
Illustration of HT Triggering and Explicit Payload Signals Identifiable By This Approach