2021-288-RUN-TIME RECONFIGURABLE ARCHITECTURE

Summary: 

Researchers in the Department of Electrical and Computer Engineering at UCLA have invented a novel scheduler architecture that enables reconfigurable architectures to run multiple operations, locally or over a network, and improve throughput and flexibility.

Background:

Advancements in semiconductor technology have resulted in exponential growth in computing performance and algorithmic development. Recently, scaling has slowed as transistor sizes approach physical limits. Conventional computing architectures, such as central processing units (CPU), are unable to keep up with the increasing requirements of modern algorithms due to their inherent architectural inefficiencies. Technologies, including application specific integrated chips (ASICs) and field programmable gate arrays (FPGAs), have helped remedy this issue, but not without drawbacks. ASICs are very expensive and time-consuming to develop  and can quickly become outdated, while FPGAs are inefficient both in terms of power consumption and area consumption. Coarse Grain Reconfigurable Architectures (CGRA) can help makeup the deficiencies experienced by ASICs and FPGAs. They are more compact, efficient, and in limited cases, offer flexibility unmatched by conventional technologies. However, more work is needed to truly realize the potential of CGRAs as well as ASICs and FPGAs.

Innovation: 

Researchers at UCLA have developed an innovative reconfigurable architecture that is able to run multiple programs and can function from a single program or multiple programs simultaneously from various hosts across a network. The invention can increase throughput and reduce latency of reconfigurable architectures while increasing flexibility thus addressing the constraints of FPGAs and CGRAs. Furthermore, hardware utilization is improved as a variety of hosts can allocate unused resources to other programs or hosts across a network. As a result of its decentralized nature, the architecture is also more resilient to hardware defects. Most crucially, the invention allows users to implement large footprint programs on relatively small reconfigurable architectures with high throughput.

Potential Applications:

• Scheduler architecture for reconfigurable architectures ASIC, FPGA, and CGRA
• Relevant to general purpose computing, signal processing, software defined radio, cognitive radio, and cybersecurity

Advantages:

• High throughput and low latency
• Greater flexibility
• More resilient to hardware defects
• Increased hardware utilization
• Enables high footprint programs implemented on small area architectures

Development-to-date: Invention was conceived and fully described

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