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Network-on-Chip (NoC) Hardware Accelerators

Abstract: This patented technology describes various configurations of Networks-on-Chip (NoCs), such as those with multiple wired and wireless links and dynamic node allocation. In some embodiments, a torus interconnect structure is employed. Advantages: Reduced network latency by offering multiple alternative communication nodes. Increased...

Published: 10/8/2024 | Inventor(s): Partha Pande, Anantharaman Kalyanaraman, Turbo Majumder

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Category(s): Technologies > Energy & Environment > Computer Hardware/Software