PAGE TITLE
Dynamic Power Management Scheme Through Swarm Intelligence
PAGE SUMMARY
As the proliferation of ubiquitous computing environments becomes a reality, the need for high speed data processing and intelligent system management increases rapidly. In particular, the need for low-power designs and power-aware system management is getting stronger. While multicore systems are deployed in many embedded system areas, an effective power management technique for multicores is not available yet. The existing power management schemes for multi-core systems employ a central power management unit (PMU) that controls the operating voltage (and frequency for DVFS) for the cores and the core connectivity fabric. The decision to scale the voltage and frequency is executed by the operating system. A centralized power management scheme does not scale well as the number of processors in an IC increases. Moreover, state of the art GPUs still operate with off-chip voltage regulators, which leads to higher reaction latency to changes in load current.
In light of these drawbacks, researchers at Drexel have developed a novel on-chip power distribution network with distributed on-chip voltage regulators(OCVR), distributed timing sensors, and a power management unit(s). The on-chip PMU self-learns and regulates the local voltages intelligently and autonomously without inducing any timing failure. The distributed OCVRs operate as a swarm to locally optimize the operating voltage to prevent timing violations on the local critical paths as well as to compensate for aging related degradation in both the load and OCVR circuits. The run-time assignment of the voltage through the particle swarm optimizer negates the effects of transistor aging, process, temperature, and power supply noise induced variation in the load circuits, voltage regulators and sensors. This distributed power management scheme can be deployed for a range of circuit families including server class high performance processor cores, computing cores for mobile applications, hardware accelerators for deep neural networks (DNN), network on chip (NoC) routers, and for large clusters of IoT sensor nodes.
APPLICATIONS
TITLE: Applications
A Dynamic Power Management Scheme For a Range of Circuit Families
=>High Performance Processor Cores
=>Hardware Accelerators for Deep Neural Networks
=>Network On-Chip Routers
=>Large Cluster of IoT Sensor Nodes
=>Graphics Processing Units
ADVANTAGES
TITLE:Advantages
Direct communication of the circuit sensory information with the system reduces execution latency
Reduction in transistor aging
Reduction in power supply noise due to variations
Reduction in power consumption and operating temperature
Reduction in the static voltage guard-band added during chip design for worst case process
Significant increase in the overall end of life of the circuit
IP STATUS
Intellectual Property and Development Status
Provisional Application Filed
PUBLICATIONS
References
D. Pathak, H. Homayoun and I. Savidis, "Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 9, pp. 2538-2551, Sept. 2017.
https://ieeexplore.ieee.org/document/7938724
Contact Information
Harshith Reddy
Licensing Manager
215-571-4290
harshith@drexel.edu