When there is a requirement for a custom logic solution, the technology chosen is typically one of either Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA). Today, FPGAs occupy only a small portion of the custom semiconductor market, hampered by high power consumption and relatively low logic capacity compared with ASICs.
Researchers at Princeton University in Princeton NJ and Queen’s University in Kingston Ontario have achieved the ultimate goal of the FPGA industry, which is to create a programmable device that can compete with ASICs in power consumption, capacity and cost. They are now completing a chip layout that will represent a total disruption in the semiconductor industry.
FPGAs based on this technology will have capabilities far beyond any conceivable extension of the architecture found in commercial FPGAs today. This new device, based on only the first in a series of innovative architectures, offers:
· 25 times higher logic capacity than cost and node comparable FPGAs
· Significantly lower (50%) power consumption than comparable FPGAs
· Retains ease of use and time-to-market advantages of programmable devices
· Compatibility with today’s CMOS processes and is manufacturable today.
This technology achieves this dramatic improvement in capability by leveraging “temporal logic folding”, or the ability to re-use logic cells at picosecond rates, through the combination of standard CMOS logic with embedded DRAM and a novel, flexible architecture.
By October 2010, researchers will be ready to release this prototype device to manufacturing. Synthesis CAD tools are available now which are able to compile generalized RTL or gate level circuits into folded logic configuration files. Once productized, this technology may be utilized in advanced systems and devices to provide ASIC like functionality at competitive price points, with very short development cycles, ensuring that this technology will displace a large portion of ASIC design wins.
For companies that either buy or develop ASICs, this technology will have a dramatic impact by through elimination of the extremely non-recurring engineering charges associated with ASIC development, and will shorten design cycles from years to months, yielding additional engineering cost reductions.
Applications:
· General purpose FPGA
· ASIC replacement technology
· Programmable logic cores for SoC, GPU and CPU
Development Status:
A prototype chip is in layout now, and will be ready for tape out by Q4 2010.
Synthesis CAD tools have been developed and are available now to take standard RTL/gate level circuits and produce folded logic configuration binaries.
A full suite of research papers and simulation results are published and available to document the full capabilities of the technology.
Commercialization Status:
PARTEQ Innovations, the technology transfer office of Queen’s University, is seeking industrial partners and/or venture capitalists interested in participating in this commercialization project.