PRISM: Physics-Informed Machine Learning for CPU Performance Modeling

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Overview of PRISM

Invention Summary:

CPU architects rely on performance models to evaluate new microarchitectural designs before hardware implementation. While cycle-accurate simulators provide highly accurate performance estimates, they require significant computational resources and can slow the exploration of large design spaces. More recent machine learning–based performance models reduce simulation time but typically predict only aggregate metrics such as cycles per instruction (CPI), offering limited insight into the underlying causes of performance bottlenecks. As a result, there remains a need for faster and more interpretable performance modeling techniques that can reduce dependence on expensive simulation data while providing actionable guidance for architectural optimization.

Rutgers researchers have developed PRISM, a physics-informed machine learning framework for CPU microarchitecture performance modeling. PRISM innovatively predicts a structured Multi-Stage CPI Stack (MSCS) vector rather than a scalar CPI, decomposing pipeline utilization into per-stage bottleneck attributions. It embeds architectural invariants as label-free training constraints enabling semi-supervised training that leverages unlabeled instruction traces, reducing reliance on costly cycle-accurate simulation labels. This novel approach allows for bottleneck-aware design optimization and parameter attribution, dramatically improving both efficiency and interpretability of CPU performance modeling.

Market Applications:

• CPU and SoC architects at semiconductor companies (Intel, AMD, NVIDIA, Qualcomm) for early-stage microarchitecture development.
• Cloud providers with custom silicon designs (Google TPU, Amazon Graviton, Microsoft Azure) for optimized chip performance.
• Integration into commercial EDA tools (Synopsys, Cadence) as a standalone or embedded performance modeling module.
• ML-accelerated design space exploration replacing or augmenting cycle-accurate simulation.
• Bottleneck-driven performance diagnosis tools embedded in existing development workflows.
• Performance modeling solutions tailored for teams with limited simulation compute resources.

Advantages:

• Structured MSCS vector prediction provides detailed per-stage bottleneck insights.
• Physics-constrained, label-free training enabling unsupervised pretraining and reducing simulation label needs by 40%.
• Supports bottleneck-aware design space exploration with formal analysis of optimization failure modes. Simulator-agnostic pipeline compatible with various cycle-level data sources.
• Improves both prediction accuracy and label efficiency compared to state-of-the-art models.

Publications:

• W. Li, A. Yazdanbakhsh, K. Paudel, S. Pandey, H. Liu, "Label-Efficient and Bottleneck-Exposing CPU Performance Modeling with Architectural Invariants," MLArchSys Workshop @ ISCA 2026. (https://openreview.net/forum?id=3QVeBa5bTe)

Intellectual Property & Development Status: Provisional application filed. Patent pending. Available for licensing and/or research collaboration. For any business development and other collaborative partnerships, contact:  marketingbd@research.rutgers.edu