Recent research in Stochastic Computing (SC) is focused on practical methods for bitstream generation, optimizing logic operations for stochastic data, and developing architectures that natively support SC. This approach has proven particularly promising in simplifying and accelerating complex computations in fields such as AI and image processing. However, conventional hardware platforms, such as FPGAs and microprocessors, do not efficiently support SC's bitwise operations and stochastic processing requirements.
GW Researchers have developed a novel field programmable architecture that supports stochastic computing (SC) as a first-class citizen. The proposed method has efficient mechanism for generating and managing true random bitstreams by using the stochastic behavior of magnetic tunnel junction (MTJs), where each bit in a stochastic data stream is processed independently. It improves system readiness, as configurations are immediately available for processing upon power-up, eliminating delays associated with loading configurations from external memory. Also, leverages use of feedback loops for precise control of MTJ switching currents and advanced post-processing mechanisms to compensate for manufacturing inconsistencies.
Fig. An overview of ESSRA
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